Delta-sigma modulators (DSMs) are one of the low-power high-resolution analog-to-digital converters (ADCs) structures, DSMs are suitable for high-resolution low-to-medium bandwidth applications, such as AM or FM radio frequencies. DSMs, which may also be written as ΔΣ modulators, use both oversampling and noise-shaping to enhance their signal-to-quantization noise-ratio (SQNR). DSMs achieve noise-shaping by a low-pass continuous-time (CT) or discrete-time (DT) loop filter consisting of several integrators. The outputs of these integrators may then be fed to a multi-bit quantizer, such as a flash ADC. The output of the flash ADC is both the DSM output and the feedback that gets subtracted from the input of the modulator. This subtraction forms a negative feedback to stabilize the loop. However, as the order of the loop filter and hence the noise-shaping is increased, the power of the quantization noise will also increase and may saturate the loop. To enhance the stability and the overall performance, a larger number of back-end quantization levels in the flash ADC may be necessary. This may mean a tradeoff between the power consumption and the overall performance because increasing the number of the quantization levels in the flash ADC will not only increase the power consumption of the flash ADC itself, but also imposes larger capacitive loading on the outputs of the loop filter elements, i.e. the integrators.
There are several techniques to replace the flash ADC quantizer in a delta-sigma loop to avoid this tradeoff. A first technique may include a voltage-controlled oscillator (VCO) based quantizer that uses time and frequency as the medium. This VCO based structure may be able to achieve high-speed and a large number of quantization levels as well as increase the order of the noise-shaping by one. However, the VCO based structure may have some disadvantages, including performance degradation from signal-to-noise plus distortion ratio (SNDR), gain variations and stability concerns.
A second technique is to replace the flash ADC in a DSM with an altered integrating quantizer similar to a classical dual-slope integrating quantizer. But the altered integrating quantizer stores the charge residue in the integrator at the end of each conversion cycle for the next conversion, thereby providing first order noise shaping. In addition, the pulse-width modulation (PWM) information from altered integrating quantizer output can be used to extend the order of the DSM. This second technique may have a few different approaches.
A first approach to the second technique of replacing the flash ADC with this type of altered integrating quantizer uses a DT switched capacitor (SC) dual-slope integrating quantizer in a 2nd order SC DSM loop. The DT SC approach may need a multibit digital to analog converter (MB-DAC) in the feedback loop and a complicated digital logic control to obtain the required resolution.
A second approach may implement the altered dual-slope integrating quantizer in CT. In this way, the DSM feedback loop can use a single-bit DAC (SB-DAC) to replace the MB-DAC. For this second approach, input for the SB-DAC in the feedback loop is the PWM signal generated by the dual-slope integrating quantizer. However, this approach may suffer from current leakage in the integrating quantizer capacitor because the value of the voltage in the capacitor must be stored during a non-fixed time for the next sampling period. This effect may introduce both quantization errors and overloading of the integrating quantizer. In addition, the digital control for this second approach is quite complicated. Both the first approach and second approach to replacing the flash ADC with a dual-slope integrating quantizer may require a complex digital control scheme to ensure a linear transfer function in the integrating quantizer.